Data Routing : a Paradigm for E cient Data - Path Synthesis andCode

This paper describes a new and eeective approach to register and interconnect optimisation, which is applicable in a dual context : to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. The key idea is to carefully optimise the way in which data is transferred between functional units. The impact on high-level synthesis will be demonstrated with a practical design from the area of telecommunications.